Single crystal silicon sensor with high aspect ratio and curvilinear structures and associated method

ABSTRACT

In one aspect, the invention provides semiconductor sensor which includes a first single crystal silicon wafer layer. A single crystal silicon structure is formed in the first wafer layer. The structure includes two oppositely disposed substantially vertical major surfaces and two oppositely disposed generally horizontal minor surfaces. The aspect ratio of major surface to minor surface is at least 5:1. A carrier which includes a recessed region is secured to the first wafer layer such that said structure is suspended opposite the recessed region.

RELATED APPLICATIONS

[0001] This application is a continuation-in-part of patent applicationSer. No. 08/449,140, filed May 24, 1995, by inventors Kurt Petersen;Nadim Maluf; Wendell McCulley; John Logan and Erno Klaassen, entitled,“Single Crystal Silicon Sensor With High Aspect Ratio and CurvilinearStructures and Associated Method”

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] The invention relates, in general, to semiconductormicroelectronic sensors, and more particularly, to single crystalsilicon sensors that include structures with diverse contours and higheraspect ratio geometries.

[0004] 2. Description of the Related Art

[0005] The electrical and mechanical properties of silicon microsensorshave been well chronicled. For example, refer to Kurt E. Petersen,“Silicon as a Mechanical Material”, Proceedings of the IEEE, vol. 70,No. 5, May 1982. Moreover, there is a large and growing body ofknowledge concerning techniques for constructing siliconmicrostructures, commonly referred to as “micromachining” See, forexample, Bryzek, Petersen and McCulley, “Micromachines on the March”,IEEE Spectrum, May 1994, pp. 20-31.

[0006] Silicon micromachining has blossomed into a vital industry withnumerous practical applications. For instance, micromachined siliconpressure and acceleration sensors have found their way into medicalinstrumentation and automobiles. The high strength, elasticity andresilience of silicon makes it an ideal base material for resonantstructures that may, for example, be useful for electronic frequencycontrol. Even consumer items such as watches, scuba diving equipment,hand-held tire pressure gages and inflatable tennis shoes may soonincorporate silicon micromachined sensors.

[0007] The demand for silicon sensors in ever expanding fields of usecontinues to fuel a need for new and different silicon microsensorsensorgeometries optimized for particular environments. Unfortunately, adrawback of traditional bulk silicon micromachining techniques has beenthat the contours and geometries of the resulting siliconmicrostructures have been significantly limited by these fabricationmethods. For example, anisotropic etching of single crystal silicon(SCS) can achieve an anisotrophy rate of 100:1 in the <100>crystallographic direction relative to the <111> direction. The resultof such anisotropic etching of SCS, however, typically will be a siliconmicrostructure with sidewalls that are inclined because of theintersection of the (100) and (111) crystallographic planes. As aresult, the contours of silicon microstructures have been limited by theorientation of the internal crystallographic planes. Thus, there hasbeen a need for silicon microsensors having structures with more diversegeometric contours.

[0008] The increasing use of microsensors to measure pressure andacceleration has spurred the development of tiny silicon platestructures used as capacitors and to produce electrostatic forces, forexample. For instance, there exist microsensors that measure capacitanceusing an array of interdigitated polysilicon plates. Similarly, thereexist microsensors that produce electrostatic forces using an array ofinterdigited plates Ordinarily, the surface areas of such plates arerelatively small since they typically are formed in a depositedpolysilicon layer. Increasing the surface area of such capacitive platesincreases their capacitance. Increasing the surface area of suchelectrostatic drive plates increases their drive capability. Hence,there has been a need for capacitive plates and electrostatic driveplates with increased surface areas.

[0009] There also is a need for improved silicon microstructures onwhich electronic circuitry can be formed. For example, metal oxidesemiconductor (MOS) circuits generally are most effective when formed in(100) silicon wafers. Unfortunately, traditional silicon micromachiningtechniques usually favor the formation of microsensors in (110) wafers.Hence, MOS circuits have not been prevalent in silicon microsensors.Moreover, in some applications there can be a need to thermally isolatea circuit formed as part of a microsensor in order to ensure optimalcircuit performance.

[0010] A problem with tuneable resonant microstructures formed frommaterials such as polysilicon or metal is that they can suffer frequencydrift over time due to internal crystal stresses that develop from usageThus, there is a particular need for a microstructure that employs ahigh-Q resonator that does not suffer from crystal stresses. It has longbeen known that SCS is an excellent base material for a resonantstructure. It is strong, flexible and highly elastic, and its singlecrystal structure makes it more resistant to performance degradation.However, tuning the resonant frequency of an SCS resonant structure canbe a challenge. Consequently, there is a need for an improved approachto the tuning of a high-Q SCS resonator

[0011] Thus, there has been a need for silicon microsensors thatincorporate structures with more diverse geometries including structureswith contours that are not limited by the crystallographic planes ofsilicon and plates with increased surface areas. There also has been aneed for silicon microsensors with structures that are better suited tothe formation of electronic circuitry. In addition, there has been aneed for silicon microstructures with improved resonant structures. Thepresent invention meets these needs.

SUMMARY OF THE INVENTION

[0012] In one aspect, the invention provides semiconductor sensor whichincludes a first single crystal silicon wafer layer. A single crystalsilicon structure is formed in the first wafer layer. The structureincludes two oppositely disposed substantially vertical major surfacesand two oppositely disposed generally horizontal minor surfaces. Theaspect ratio of major surface to minor surface is at least 5:1. Acarrier which includes a recessed region is secured to the first waferlayer such that said structure is suspended opposite the recessedregion.

BRIEF DESCRIPTION OF THE DRAWINGS

[0013]FIG. 1 is a perspective fragmented view of a portion of a siliconsensor in accordance with an embodiment of the invention;

[0014]FIG. 2 is a perspective view of an array of high aspect ratiointerdigitated vertical plates used either for capacitance pick-up orelectrostatic force in accordance with an embodiment of the invention;

[0015]FIG. 3 is a perspective fragmented view of a portion of a siliconsensor in accordance with an embodiment of the invention;

[0016]FIG. 4 is a cross-sectional perspective view of a curvilinearreleased structure in accordance with an embodiment of the invention;

[0017]FIG. 5 is a perspective view of a portion of suspended structuresand a portion of a fixed structures used as a variable capacitor inaccordance with an embodiment of the invention;

[0018]FIG. 6 is a top elevation view of an acceleration sensor inaccordance with an embodiment of the invention;

[0019]FIG. 7 is a top elevation view of a variable frequency, high-Qresonator in accordance with an embodiment of the invention;

[0020] FIGS. 8A-8G illustrate fabrication process flow in accordancewith the invention;

[0021] FIGS. 9A-9D are side cross-section views of a device infabrication illustrating fabrication process flow during production of asuspended or a released structure in accordance with the invention;

[0022]FIG. 10 is a side cross-section view of a device in fabricationshowing a first alternative fabrication process flow during productionof a released structure in accordance with the invention;

[0023]FIG. 11 is a side cross-section view of a device in fabricationshowing a second alternative fabrication process flow during productionof a released structure in accordance with the invention;

[0024]FIG. 12A-12B are a top elevation and side cross-section views of asuspended resonator structure in accordance with the invention; and

[0025]FIG. 13 is a top elevation view of an alternative suspendedresonator structure in accordance with the invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

[0026] The present invention comprises a single crystal silicon sensorwith curvilinear structures and high aspect ratio structures and anassociated method of manufacture. The following description is presentedto enable any person skilled in the art to make and use the invention.Descriptions of specific applications are provided only as examples.Various modifications to the preferred embodiment will be readilyapparent to those skilled in the art, and the general principles definedherein may be applied to other embodiments and applications withoutdeparting from the spirit and scope of the invention. Thus, the presentinvention is not intended to be limited to the embodiments shown, but isto be accorded the widest scope consistent with the principles andfeatures disclosed herein.

[0027] Referring to the illustrative drawings of FIG. 1, there is showna partial, fragmented, perspective view of a portion of a siliconmicrosensor 20 in accordance with a presently preferred embodiment ofthe invention. The microsensor 20 includes a first single crystalsilicon (SCS) wafer layer 22 bonded to a carrier 24. First and secondbeams 26 and 28 depend from the first layer 22. The phantom lines inFIG. 1 represent surfaces that are hidden from view. The two beams 26and 28 are suspended over a recessed region 30 of the carrier 24, suchthat the beams can move relative to the carrier 24.

[0028] Beam 26 includes a pair of oppositely facing major verticalsurfaces 26-1 and a minor vertical distal end surface 26-2 and furtherincludes a pair of opposite facing horizontal surfaces 26-3. Similarly,beam 28 includes a pair of oppositely facing major vertical surfaces28-1 and a pair of oppositely facing horizontal surfaces 28-2. It willbe appreciated that only one of each of the major vertical surfaces in28-1 and only one of the horizontal surfaces 28-2 are visible in thedrawing. In addition, the second beam 28 has a seismic mass 32 securedto a distal end thereof.

[0029] In operation, each of the two beams deflect in the plane of thefirst layer 22 as indicated by arrows 22′ but cannot deflect in adirection generally perpendicular to the plane of the first layer 22 asindicated by arrows 22″ This ability to flex in the plane of the firstlayer 22 but not out of the plane of the first layer 22 results from theaspect ratio of the beams; the ratio of their vertical heights H₁ and H₂respectively to their widths, W₁ and W₂, respectively.

[0030] Referring to the illustrative drawings of FIG. 2, there is shownan array of interdigitated plate structures in accordance with anembodiment of the invention. Fixed plate structures 42, 44 and 46 areintegrally secured to a fixed semiconductor structure 48 Single crystalsemiconductor plate structures 50, 52 and 54 all depend from a moveablesilicon structure 56. The direction of movement of the moveable platestructures 50, 52 and 54 relative to the fixed plate structures 42, 44and 46 is indicated by the arrow 58.

[0031] Each of the fixed plates and the moveable plates can be doped tomake them conductive. In one embodiment, the dopant is boron and thedopant concentration is between 10 ¹⁶/cm³ to 10 ²⁰/cm³. Alternatively,phosphorus or arsenic can be used as the dopant, for example. Thestructure illustrated in FIG. 2 can operate as a series of parallelcapacitors. The amount of total capacitance depends upon the degree ofoverlap of the interdigitated fixed plates 42, 40 and 46 with themoveable plates 50, 52 and 54. The movement of the moveable plates alongthe axis indicated by arrow 58 determines the amount of overlap.Alternatively, the structure in FIG. 2 also can serve as anelectrostatic drive mechanism. In that case, a voltage differentialbetween the fixed plates 42, 44 and 46 and the moveable plates 50, 52and 54 can exert an electrostatic force which can induce the moveableplates to alter the amount of overlap with the fixed plates.

[0032] It will be appreciated that the surface areas of theinterdigitated plates can have an important bearing up on thecapacitance between plates of the interdigitated structure in FIG. 2.Likewise, the amount of overlapping surface area can also have animportant bearing on the amount of electrostatic force that can beexerted by a structure like that in FIG. 2.

[0033] Thus, to the extent that the current invention permits theproduction of plate devices that have relatively high aspect ratios(plate height/plate width), the invention facilitates the production ofmore efficient interdigitated plate capacitor arrays and interdigitatedplate electrostatic drive arrays.

[0034] Referring to the illustrative drawings of FIG. 3, there is showna perspective fragmented view of a portion of a SCS silicon microsensor70 in accordance with the embodiment of the present invention. Themicrosensor 70 includes a first SCS layer 72 bonded to carrier 74. Abeam 76 having a seismic mass 78 formed on a distal end thereof dependsfrom the first layer and is suspended over a recessed region 80 of thecarrier 74 such that the beam 76 and its mass 78 can move relative tothe carrier 74.

[0035] The aspect ratio (vertical height/horizontal width) of the beamis large enough such that it can deflect in the plane of the first layer72 indicated by arrow 72′ but cannot deflect out of the plane of thelayer 72 indicated by arrow 72″. The processing techniques, describedbelow, permit the fabrication of a beam with an aspect ratio of at least20:1.

[0036] Moreover, since the processing techniques described below permitdeep etching independent of crystallographic directions, the beam 76 andthe seismic mass 78 can be formed in (100) silicon wafers is suitablefor fabrication of MOS circuits. Hence, a MOS circuit can be readilyformed in the upper face 82 of the seismic mass using standardsemiconductor processing techniques.

[0037] Referring to the illustrative drawings of FIG. 4, there is showna cross-sectional view of a fully released SCS structure 90 still seatedwithin a recess 92 which has been etched into a first SCS wafer layer94, which is bonded to a carrier 96 in accordance with invention. Inparticular, the released structure 90, which is shown in cross-section,is cylindrical in shape. It has a curvlinear outer circular(circumference) defined by the etched away region 92. In addition, ithas a circular (curvilinear) inner core defined by etched away region98. The inner core of the released structure surrounds an upstandingportion of the carrier 96 which, for example, can serve as a stabilizingmember or an axel.

[0038] Thus, it will be appreciated that the fabrication techniquesdescribed below can be used to create etch patterns which arecurvilinear in shape. The term curvilinear as used herein shall meanbending without angles. A curvilinear structure is one which hasportions thereof which bend without precise angles, although otherportions may comprise straight segments or angled joints. Examples ofcurvilinear structures include circles, ellipses and spirals.

[0039] Referring to the illustrative drawings of FIG. 5, there is showna perspective partial view of a variable capacitor 100 in accordancewith an embodiment of the invention. The variable capacitor comprises afixed structure 102 and a moveable structure 104 The fixed structureincludes a capacitor plate 106 which is interdigitated with parallelplates 108 and 110 which depend from the moveable structure 104. It willbe appreciated that the moveable structure 104 depends from a fixed SCSwafer layer 112 and that the entire moveable structure is suspended overa carrier (not shown). Moreover, it will be appreciated that thecapacitor may have additional plates which are not shown The processesfor producing the moveable structure will be appreciated from thediscussion below

[0040] The moveable structure 104 also includes thermal actuators 114and 116. The thermal actuators contain circuitry 118 and 120 which, whenelectric current is passed through them causes the thermal actuators toheat up resulting in expansion of the SCS beams in which they aredisposed. The heating of the beams and their expansion causes a movementof the capacitive plate 108 and 110 toward the fixed structure 102. As aresult, there is greater overlap of the plates 108 and 106 and of theplates 106 and 110. The increased overlap results in an increasedcapacitance. Since the current invention permits the fabrication ofstructures such as those shown in FIG. 5 using (100) silicon, complexMOS used to monitor capacitance between the plates 108 and to controlthe flow of current in the thermal actuators can be disposed directly onthe moveable structure. Furthermore, since the processing techniquesdescribed below permit the production of plates with relatively highaspect ratios (height/width) a large number of capacitive plates can besqueezed in close to each other, and the increased height afforded bythe deep etching process ensures that greater surface area will beexposed when the plates are filly engaged.

[0041] Referring to the illustrative drawings of FIG. 6, there is showna top elevation view of a SCS accelerometer in accordance with a currentembodiment in the invention. A first SCS wafer layer 122 has deepgrooves 124 formed therein to define a suspended beam 126 elongatedmechanical guidance beams 128 and a plurality of interdigitatedelectrostatic plates 130 and 132. The released structure includes aproof mass 134. Piezoresistors (not shown) are disposed at the foot ofthe beam 126 at the point of highest stress. Interconnect pads 136 areused to make of-chip electrical connections to the accelerometer 120.

[0042] It will be appreciated that the suspended structures aresuspended over a carrier (not shown) and can move freely relative to thecarrier. The sense-beam 126 and the interdigitated plates 130 and 132can have relatively large aspect ratios (height/width). This relativelyhigh aspect ratio can prevent the beam from twisting due to off-axisacceleration. As explained above, a high aspect ratio beam can movereadily within the plane of the first wafer 122 but cannot move out ofthat plane. Moreover, the relatively high aspect ratio of theinterdigitated plates permits increased capacitive coupling and alsoallows for increased electrostatic force. The elongated beams 128 serveas stabilizers They flex much more readily than the short sense-beam126. Hence, they are not used for actual measurements of stress andtherefore acceleration However they are used to stabilize the movementof the relatively large collection of suspended structures.

[0043] In operation, the short sense-beam will flex in a directionindicated by arrow 126′. The collection of interdigitated plates 130 and132 will either experience an increase in overlap capacity or a decreasein overlap capacity depending upon the direction of deflection of thesense-beam 126. Thus, the capacitive plates can be used to sense adegree of deflection of the sense-beam Alternatively, the interdigitatedbeams can be used to apply an electrostatic force sufficient to overcomethe deflection of the beam. The degree of electrostatic force necessaryto overcome such deflection is related to the acceleration experience bythe accelerometer 120. The circuitry used to determine the amount offlexure of the sense-beam, and the amount of overlap of theinterdigitated plates 130 and 132 or, alternatively, to apply acountervailing electrostatic force, employ techniques well known tothose skilled in the art and that are not part of the present invention.Hence they need not be described herein.

[0044] Referring to the illustrative drawings of FIG. 7, there is showna top elevation view of a variable frequency, high-Q single crystalsilicon resonator. The dark regions represent deep channels or trenchesformed through the deep reactive ion etch process described below. Theresonator 140 includes a resonant beam 142 disposed between a pair ofelectrostatic deflection electrodes 144 and 146. A plurality of beamsarrayed on either side of the beam 146 serve as thermal actuators 148and 150. An enlarged head portion 152 has a plurality of plate elementswhich are interdigitated with complementary plate elements of a fixedstructure 156. A piezoresistive element is formed in the most highstress region of the resonator 140 near its base that interconnects withthe single crystal silicon first layer.

[0045] In operation, the electrostatic deflection electrodes 144 and 146apply an AC voltage between them which excites the beam 142 to resonate.The frequency of resonation of the beam 142 can be detected using thepeizoresistive sense element 158. The resonant frequency of the beam canbe altered by changing the stiffness of the beam. The array of thermalactuators 148 and 150 can be used to selectively tune the resonantfrequency of the beam.

[0046] Specifically, by differential heating of the thermal actuators148 and 150, a coarse stiffening of the beam 142 can be achieved. Thiscoarse stiffening of the beam 142 achieves a coarse tuning of itsresonator. The thermal actuator achieves stiffening of the beam bypressing against the head plate 152. This pressing against the headplate stiffens the beam. The array of interdigitated plateselectrostatic force plates 154 are used to achieve fine tuning of theresonant frequency of the beam. The amount of electrostatic forceapplied by using the array of plates 154 can be controlled with relativeprecision. Hence, the thermal actuators 148 and 150 are used for coarsetuning, and the electrostatic force plates are used for fine tuning. Inthis manner, a relatively high-Q resonator can be achieved. A high-Qresonator is one with an accurate and narrow frequency band.

[0047] The process for fabricating a silicon microsensor in accordancewith a presently preferred embodiment of the invention is explained withreference to FIGS. 8A-G. The current embodiment employs two siliconwafers The process results in the formation of a prescribed SCSmicrostructure as an integral portion of a first wafer. A second waferserves as a carrier for the first wafer as explained below.Alternatively, the carrier can be formed of glass (pyrex), for example.It will be understood, of course, that although the following discussionrefers to only two wafers, the principles can be applied to theformation of a microsensor comprising a stack of more than two wafers.

[0048] In FIG. 8A, the second wafer is patterned with a photoresistwhich defines a recessed region to be formed in the second wafer. InFIG. 8B, the recessed region is formed in the second wafer usingstandard semiconductor techniques such as, for example, plasma etching,wet-etching with KOH or other silicon etchants, or differential oxidegrowth. The recessed region can have any arbitrary geometry and can haveany required depth, from <0.1 micron to >100 microns, for example.

[0049] It should be appreciated that the recessed region need not have asingle, uniform depth. For example, several standard silicon etch stepsmay be employed to produce several different depths that can be used fordifferent mechanical functions. Moreover, the second wafer surface canbe either bare silicon or it can be coated with an oxide layer. Also,the base of the recessed region can be either bare silicon, oxidizedsilicon, doped silicon, or it can be coated with any other thin filmcapable of withstanding subsequent wafer bonding and processingtemperatures.

[0050] In FIG. 8C, the patterned surface of the second wafer is bondedto the first wafer by silicon fusion bonding (or direct bonding)process. Fusion bonding techniques are well known For example, refer to,K. E. Petersen, D Gee, F. Pourahmadi, R. Craddock, J. Brown, and L.Christel, “Surface Micromachined Structures Fabricated with SiliconFusion Bonding,” Proceedings, Transducers 91, June 1991, at pp. 397-399which is expressly incorporated herein by this reference. In a currentlypreferred fusion bonding technique, the first and second wafers are madehydrophilic. That is, they are treated with an agent such as hot nitricacid or a hot sulfuric acid and hydrogen peroxide solution or anotherstrong oxidant, that causes water to adhere to them. The two wafers thenare placed in an oxidizing atmosphere at a temperature of 400° C.-1200°C. for approximately one hour.

[0051] The silicon fusion bonding technique described above bonds thefirst and second wafers together without the use of an intermediate gluematerial that could have a different coefficient of thermal expansionthan the single crystal silicon wafers. Furthermore, fusion bonding canbe performed in which oxide or nitride layers have been formed in thebonded surfaces of one or both of the wafers.

[0052] As an alternative to fusion bonding, for example, the first andsecond wafers can be adhered together with an adhesive such as aphotoresist. As another alternative, the first and second wafers canhave their major surfaces coated with a metal layer used to alloy thewafers to one another In the event that a glass carrier is used insteadof the second silicon wafer, the first wafer can be anodically bonded tosuch glass carrier.

[0053] In FIG. 8D, the first wafer is thinned and polished to thethickness required by the particular application. Alternatively,electrochemical etching can be used to thin the wafer. In FIG. 20E, anynecessary circuits or other thin film depositions and patterning can beperformed using standard silicon processing techniques. Since the fusionbond is typically annealed at high temperature (>900° C.), there arefew, if any, limitations imposed on the circuit processing temperaturesto avoid harming the bond. Moreover, since the subsequent etch processdiscussed below is a dry etch, on-chip circuits can be protected with adeposited oxide layer or a silicon nitride layer of about 15 micronsthickness or by photoresist.

[0054] In FIG. 8F, the first wafer is patterned for a Deep Reactive IonEtching (DRIE) step which defines the regions of the “top” wafer to beetched. DRIE techniques have become increasingly well known. Forexample, refer to: V A. Yunkin, D. Fischer, and E. Voges, “HighlyAnisotrophic Selective Reactive Ion Etching of Deep Trenches inSilicon,” Microelectronic Engineering, Vol. 23, 1994, at 373-376; C.Linder, T. Tschan, N F. de Rooij, “Deep Dry Etching Techniques as a NewIC Compatible Tool for Silicon Micromachining,” Proceedings, Transducers'91, June 1991, at 524-527; C. D Fung and J. R. Linkowski, “Deep Etchingof Silicon Using Plasma,” Proceedings of the Workshop on Micromachiningand Micropackaging of Transducers, Nov. 7-8, 1984, at 159-164; and J. W.Bartha, J. Greeschner, M Puech, and P, Maquin, “Low Temperature Etchingof Si in High Density Plasma Using SF₆/O₂ ,” MicroelectronicEngineering, Vol. 27, 1995, at 453-456. Reactive Ion etch equipment nowallows the etching of holes or trenches which are very deep (>100microns), while maintaining high aspect ratios (the ratio between thedepth of the etched region and the width of the etched region. It hasbeen found that this equipment is capable of at least 20:1 aspect ratiosfor trenches as deep as 300 microns.

[0055] DRIE, in essence, involves a synergistic action between chemicaletch and ion bombardment. Impinging energized ions chemically react withthe silicon surface. The DRIE process advantageously etches in thevertical direction at a much higher rate than in the lateral direction(e.g., anisotropically) regardless of silicon crystal planes or crystalorientation. As a result, relatively deep substantially verticaltrenches or slots can be formed in the SCS first wafer. Thesesubstantially vertical trenches or slots can be formed anywhere in thefirst wafer regardless of crystallographic orientation within the wafer.Consequently, high aspect ratio structures such as capacitive orelectrostatic plates can be formed, and arbitrarily contoured structuressuch as circles, ellipses and spirals can be formed.

[0056] In FIG. 8G, a DRIE process is used to etch completely through thefirst wafer. The DRIE etching step mechanically “releases” the SCSmicrostructures formed in the first wafer, which are then free to moverelative to the second wafer. Suspended plate/beam structures withaspect ratios (height/width) of up to 20:1 have been fabricated usingthe DRIE processes described below.

[0057] In one presently preferred approach to DRIE etching, high densityplasma provides the basis for the high silicon etch-rate (5 μm/min.).The etching chemical is SF₆ at 2.5 pascals of pressure. A layer of SiO₂or a Low Temperature Oxide mask serves as the patterning mask describedin connection with FIG. 20F. A cryogenically cooled chuck, holding thewafer at approximately −100° C., causes the condensation of a very thinprotective layer on the side walls of etched grooves. This masks thesidewalls, resulting in high aspect ratios (>15:1) even for very deepgrooves. Oxygen additive gas plus CHF₃ additive gas help provide highSi/SiO₂ etch-rate ratios (>300:1) so simple 1 μm thick thermal oxide canbe used as a mask for grooves etched at least as deep as 300 μm. The“micromachining etch tool” available from Alcatel which has a place ofbusiness in San Jose, Calif. can be employed to perform the CryogenicDRIE.

[0058] In an alternative DRIE process, an inductively coupled plasmasource etches the silicon using photoresist as a mask. Polymerization ofthe photoresist mask on the sidewalls of the etched trenches slows thelateral etch rate and allows high anisotropy The etching chemical is SF₆at 50 millitorrs. Oxygen additive gas and fluorinated gas available fromSurface Technology Systems help provide high Si/photoresist etch-rateratios. A six micron photoresist serves as the patterning mask discussedin reference to FIG. 20F The photoresist selectivity is approximately50:1, which makes it possible to etch to depths of 300 μm with about 6μm of resist. The “multiplex RIE system”, available from SurfaceTechnology Systems (STS) which has a place of business in Palo Alto,Calif. can be employed to perform inductively coupled plasma DRIE.

[0059] Referring to the exemplary drawings of FIGS. 9A-9D, there areshown side cross-sectional views illustrating fabrication process flowduring production of an encapsulated suspended structure and anencapsulated released structure in accordance with the invention. Itwill be understood that many details of the process steps described withreference to FIGS. 8A-8G are used during the fabrication steps describedwith respect to FIGS. 9A-9D. These process details will not bereiterated with reference to FIGS. 9A-9D, although they may be employed.

[0060] The encapsulation of the high aspect ratio structures inaccordance with the present invention advantageously isolates thestructures from many environmental effects such as humidity, forexample. This isolation can be important since changes in humidity, forinstance, can alter the resonant frequency of resonant structures.Moreover, the enclosure of such a structure affords the opportunity tofill the cavity in which the structure resides with a viscous fluid suchas air or nitrogen which can dampen oscillations and thereby influencethe resonant frequency. Conversely, the cavity can be set to a vacuumpressure in order to reduce damping. Note that single crystal silicon isa highly advantageous material for use in resonant devices because itslow internal stresses and crystalline structure means that there isrelatively little internal damping. As another alternative, for example,the cavity can be pressurized at an elevated pressure using helium orargon for effective cooling of the structure in case it is being heated.Thus, in addition to adjusting the resonant frequency, the damping ratioof a vibrating element and thermal conductivity within an enclosedcavity, can be altered as well.

[0061] In FIG. 9A, upper recess 204 is etched in an single crystalsilicon (SCS) middle wafer 200, and lower recess 206 is etched in thesame SCS wafer 200. In a current embodiment, the upper and lowerrecesses 204 and 206 are circular. An upper structure 210 upstandswithin the upper recess 204 A lower structure 212 upstands within thelower recess 206. Next, a lower wafer 214 is bonded to the SCS middlewafer 200 so as to enclose the lower recess 206. The lower wafer 214 isbonded to the upstanding or distal end of the lower upstanding structure212 within the lower recess 206. The lower wafer 214, for example, canbe single crystal silicon. However, as explained above with respect toFIGS. 8A-8G, other materials such as glass (pyrex) may be employed forthe lower wafer 214 The lower wafer 214 may be grinded or polished to adesired thickness.

[0062] In FIG. 9B, a deep reactive ion etch (DRIE) process is employedto produce a high aspect ratio channel 216 which results in a suspendedstructure 218 surrounded by such high aspect ratio channel 216. Thesuspended structure 218 is suspended from the lower upstanding structure212 which is attached to the lower wafer 214. The lower upstandingstructure, therefore, anchors a lower end of the suspended structure 218to the lower wafer 214. The channel 216, for example, can be circularwhich results in the formation of a generally cylindrical suspendedstructure 218. It will be appreciated, however, that a circular channelis just one of many possible channel shapes as explained below Next, anupper wafer 220 is bonded to the wafer 200 enclosing the suspendedstructure 218 between the upper and lower wafers 220 and 214. The upperupstanding structure 210 has been etched so that its upper or distal endis below the upper surface of the middle wafer 200. As a result, whenthe upper wafer 220 is bonded to the middle wafer 200, there is a gapbetween the upper upstanding structure 210 and the upper wafer 220. Anupper or distal end of the suspended structure 218, is not unattached tothe upper wafer 220 and is free to move about. The suspended structure218 si disposed within a cavity defined by the etched recesses 204 and206 and by the DRI etched channel 216 The lower upstanding structure 212anchors the suspended structure 218 to the lower wafer 214 within thecavity. As illustrated in FIGS. 1, 3, 6, 12A-12B and 13, the lowerupstanding structure 212 can be constructed to be a flexible member,such as a spring or a beam, for sensor or actuator applications. Also,the suspended structure 218 may be encapsulated in an environment,gaseous or near vacuum, in which the bonding of the upper wafer 220 maytake place.

[0063]FIGS. 9C and 9D illustrate alternative etches that may beperformed at this stage of the fabrication process. In FIG. 9C, an etch222 through the lower wafer 214 can be performed to free the suspendedstructure 218 and thereby produce a released structure 218′ whichincludes the former suspended structure plus a released portion 224 ofthe lower wafer 214. The channel 222 can be circular, for example, orcan be made in other varied and complex shapes consistent with theinvention. Also, note that the released wafer portion 224 is an integralpart of the released structure 218′ of FIG. 9C In FIG. 9D, a hole 226 isetched in the lower wafer 220. The hole 226, for example, can be used tointroduce a gas into the cavity 228 surrounding the suspended structure218 and/or to pressurize the cavity 228. A fluid in the cavity 228, forexample, might be used to dampen the vibration of the suspendedstructure 218. After the introduction of the gas or fluid or after thepressurization is complete, the hole may be sealed using and adhesive oran epoxy sealant for example.

[0064] As an alternative to the overall fabrication process describedabove with respect to FIGS. 9A-9D, instead of forming recesses in amiddle wafer, recesses could be formed in upper and lower (outer)wafers. For example, referring to the illustrative drawings of FIG. 10,there is shown a side cross-sectional view of an alternative multiplewafer device with an SCS released structure 218″ Upper and lower wafers220′ and 214′ have recesses formed in them as shown. The recess in theupper wafer 220′ defines an upper upstanding structure 210′. The recess206′ in the lower wafer 214′ defines a lower upstanding structure 212′.A middle wafer 200′ that has a channel 216′ formed by a deep reactiveion etch is bonded between the upper and lower wafers 214′ and 220′.Thus, the released structure 218′ is disposed within a cavity defined bythe etched recesses 204′ and 206′ and by the DRI etch channel 216′. Theactual process steps in, accordance with the invention, that produce thestructure of FIG. 10 will be appreciated by those of ordinary skill inthe art from the explanation above relative to FIGS. 9A-9D and need notbe set forth in detail herein.

[0065] Another alternative to the overall fabrication process describedabove involves the etching through both upper and lower wafers in orderto release a structure formed from a middle wafer. Referring to theillustrative drawing of FIG. 11, for example, there is shown a sidecross-sectional view of another alternative multiple wafer device withan SCS released structure 218′″. The middle wafer 200″ is etched in amanner similar to the wafer 200 of FIGS. 9A-9D. In particular, a channel216″ is formed by deep reactive ion etching. However, an upperupstanding structure 210″ of the wafer 200″ of FIG. 11 is bonded to anupper wafer 220″ Hence, in order to release the structure 218′″, achannel 222″ is etched in a lower wafer 214″, and a channel 228″ isetched in the upper wafer 220″. The actual process steps in, accordancewith the invention, that produce the structure of FIG. 11 will beappreciated by those of ordinary skill in the art from the explanationabove relative to FIGS. 9A-9D and need not be set forth in detailherein.

[0066] The released and suspended structures produced according to thefabrication processes described above can be quite complex. For example,although the exemplary structure in FIGS. 8A-8G, 9A-9D have generallycylindrical contours, more complex structures such as a gear could beproduced. Such a gear, for example could be formed with high aspectratio gear teeth and could be encapsulated within a pressurized or fluidfilled chamber. Moreover, for example, the suspended structures of FIGS.1, 3 and 5, the acceleration sensor of FIG. 6, the resonator of FIG. 7or the resonators of FIGS. 12A-12B or of FIG. 13 can be produced by theabove processes.

[0067] Referring to the illustrative drawings of FIGS. 12A-12B, thereare shown a top cross-sectional view and a side cross-sectional view ofan alternative embodiment of a high aspect ratio encapsulated SCSresonator 230 in accordance with the invention. The resonator 230 isenclosed within a chamber or cavity 236 bounded by substantiallyvertical walls 241-244 formed in a middle SCS wafer 234 which isdisposed between an upper wafer 238 and a lower wafer 240. The resonator230 includes an array of interleaved high aspect ratio plates 232-1 and232-2. The illustrative drawing of FIG. 12B shows a side cross-sectionalview of the SCS resonator 230 along line 12B-12B of FIG. 12A. Referringto FIG. 12B, the plates 232-1 and 232-2 are suspended from the middleSCS wafer 234 within the chamber 236 between a top wafer 238 and abottom wafer 240. More particularly, a first set of plates 232-1 issuspended from a first support member 246 integral anchored to a wall242 of the middle wafer 234 within the chamber 236, and a second set ofplates 232-2 is suspended from a second support member 247 anchored to awall 244 of the middle wafer 234 within the chamber 236. The first andsecond walls 242 and 244 are disposed opposite an facing each otherwithin in the cavity 236

[0068] Specifically, the first set of plates 232-1 depend from a firstsupport member 246 that is anchored to the first wall 242.Alternatively, the first set of plates could be suspended directly fromthe first wall 242. The second set of plates 232-2 depend from a secondsupport element 248 which is suspended from a high aspect ratio springstructure 250. The spring structure, in turn, is suspended from thesecond wall 244 by a second support member 247. The spring structure 250includes first and second angled members 251 and 253. Each respectiveangled member 251 and 253 includes a respective first segment 251-1 and253-1. Each respective angled member 251 and 253 also includesrespective second segments 251-2 and 253-2. A respective first end ofeach first segment 251-1 and 253-1 is integrally secured to the secondsupport member 247. A respective first end of each second segment 251-2and 253-2 is integrally secured to third support member 248 Respectivesecond ends of the first and second segments 251-1 and 251-2 of thefirst angled member 251 are integrally joined together at an acuteangle. Likewise, respective second ends of the first and second segments253-1 and 253-2 of the second angled member 253 are integrally joinedtogether at an acute angle.

[0069] The illustrative drawing of FIG. 13 shows a perspective view ofanother alternative suspended SCS resonator 310 in accordance with theinvention. It will be appreciated that the suspended structure of FIG.13, is formed in a middle wafer sandwiched between an upper and a lowerwafer and is disposed within a cavity. Although neither the middle,upper nor lower wafers nor the cavity are shown. The resonator 310includes a first set of interleaved high aspect ratio plates 312-1 and312-2 The resonator 310 includes a second set of interleaved high aspectratio plates 314-1 and 314-2. The resonator also includes a springstructure 316 which includes elongated segments 317-1 and 317-2 whichdefine a space or gap 319 between them. Plates 312-1 depend from a firstsupport member 318 anchored to a middle wafer (not shown) at side 320.Plates 312-2 depend from a first side of the spring 316. Plates 314-1depend second support member 322 anchored to a middle wafer (not shown)at side 321. Plates 314-2 depend from a second side of the spring 316.The spring 316 is anchored within the cavity (not shown) at its distalends 324-1 and 324-2. Integrated circuits 326-1, 326-2, 326-3 and 326-4can be formed on the surfaces of the suspended resonator 310 asindicated

[0070] An advantage of producing integrated circuits directly uponmechanical parts, such as a spring or interleaved plates, is improvedparameter testing. For example, a diode or bipolar transistor formed ona mechanical part can be used to sense temperature which may influencemechanical behavior of the part. Another advantage is area savings sinceboth the moving part and the integrated circuit are formed in the sameportion of the device. Still another advantage is reduction or avoidanceof parasitics. For instance, when circuit elements are distanced frommechanical structures, there is an increased risk of losses due toparasitics due to high frequency inductance effects or capacitanceeffects.

[0071] The resonators of FIGS. 12A-12B and FIG. 13 can be produced usingprocesses illustrated in FIGS. 8A-8G and in FIGS. 9A-9D For example,recesses can be etched in the top and bottom of a middle wafer Therecessed region can be etched using DRIE process can be employed toproduce the high aspect ratio interleaved plates and high aspect ratiospring structures Integrated circuits can be fabricated on the suspendedstructure using conventional semiconductor fabrication techniques.

[0072] The operation of the resonators 230 and 310 depends upon theirimplementation and purpose. For example, the resonator 230 or 310 can beimplemented so that the spring member 250 or 316 flexes in response toelectrostatic forces between the plates. The flexure of the spring canbe sensed in order to provide a measure of the electrostatic forces.Alternatively, for instance, the resonator 230 or 310 can be implementedso that the spring member flexes in response to an acceleration force.This flexure changes the overlap of the plates which can alter thecapacitance between them. This capacitance change can be sensed in orderactuate some other device (not shown) which is controlled by theresonator. As yet another alternative, for example, the spring 250 or316 can be fabricated to have a precise resonant frequency. The springcan be stimulated to vibrate at its resonant frequency The capacitancebetween the plates also will vary at the resonant frequency of thespring. This capacitance change can be used to tune other electroniccircuits (not shown) to the resonant frequency of the spring. Thus,there are numerous potential applications of the resonator of FIGS.12A-12B and 13

[0073] It will be appreciated that there are many possible variations tothe SCS resonator of FIGS. 12A-12B and 13 consistent with the invention.For instance, the spring may be “U” shaped instead of “V” shapedAlternatively, the spring may comprise a simple beam or multiple beams;or it may comprise a more complex beam(s) which has undulations “˜”along its length so as to define a meandering path. Furthermore, thenumber of plates may vary, and the amount of plate overlap may vary aswell In addition, the gap between plates may be uneven such that oneside of a plate is closer to an adjacent plate than is the opposite sideof such plate.

[0074] While specific embodiments of the invention have been describedand illustrated, it will be appreciated that modification can be made tothese embodiments without departing from the spirit of the invention.Thus, the invention is intended to be defined in terms of the followingclaims.

What is claimed is:
 1. A semiconductor sensor comprising: a first singlecrystal silicon wafer layer; a single crystal silicon structure formedin said first wafer layer and including two oppositely disposedsubstantially vertical major surfaces and including two oppositelydisposed generally horizontal minor surfaces wherein the aspect ratio ofmajor surface to minor surface is at least 5:0; and a carrier includinga recessed region, wherein said carrier is secured to said first waferlayer such that said structure is suspended opposite the recessedregion.
 2. The sensor of claim 1 , wherein said carrier includes asilicon wafer layer; and wherein said first layer and said carrier arefusion bonded together.
 3. The sensor of claim 1 wherein said firstlayer is formed of <100> oriented silicon crystal.
 4. The sensor ofclaim 1 wherein the aspect ratio of major surface to minor surface is atleast 20:1.
 5. The sensor of claim 1 wherein said structure is a beamsecured at only one end thereof to said first wafer layer.
 6. The sensorof claim 1 wherein said structure is a beam secured at one end thereofto said first wafer layer and including a seismic mass at the other endthereof.
 7. The sensor of claim 1 wherein said structure is a beamsecured at one end thereof to said first wafer layer and including anelectronic circuit formed in the other end thereof.
 8. The sensor ofclaim 1 , wherein said first layer is formed of <100> oriented siliconcrystal; and wherein said structure is a beam secured at one end thereofto said first wafer layer and including an electronic circuit formed inthe other end thereof.
 9. The sensor of claim 1 wherein said structureis a beam secured at one end thereof to said first wafer layer andincluding a plurality of vertical plates formed in the other endthereof.
 10. The sensor of claim 1 , wherein said structure is a beamsecured at one end thereof to said first wafer layer and including aplurality of vertical plates formed in the other end thereof; andwherein said vertical plates have an aspect ratio of at least 10:1. 11.The sensor of claim 1 , wherein said structure is a beam secured at oneend thereof to said first wafer layer and including a plurality ofvertical plates formed in the other end thereof and further including anelectronic circuit formed in the other end thereof.
 12. The sensor ofclaim 1 , wherein said first layer is formed of <100> oriented siliconcrystal; and wherein said structure is a beam secured at one end thereofto said first wafer layer and including a plurality of vertical platesformed in the other end thereof and further including an electroniccircuit formed in the other end thereof.
 13. The sensor of claim 1 ,wherein said first layer is formed of <100> oriented silicon crystal;wherein said structure is a beam secured at one end thereof to saidfirst wafer layer and including a plurality of vertical plates formed inthe other end thereof and further including an electronic circuit formedin the other end thereof, and wherein said vertical plates have anaspect ratio of at least 10:1.
 14. The sensor of claim 1 wherein saidstructure is a beam secured at both ends thereof to said first waferlayer.
 15. The sensor of claim 1 wherein said structure is a platesecured at only one end thereof to said first wafer layer
 16. Asemiconductor sensor comprising: a first single crystal silicon waferlayer; a curvilinear single crystal silicon structure formed in saidfirst wafer layer and including two generally opposite facing firstsubstantially vertical surface portions and two generally oppositefacing first generally horizontal surface portions; and a second singlecrystal wafer layer including a recessed region wherein said secondwafer layer is secured to said first wafer layer such that saidstructure is suspended opposite the recessed region
 17. The sensor ofclaim 16 wherein said first wafer layer and said second wafer layer arefusion bonded together.
 18. The sensor of claim 16 wherein said firstlayer is formed of <100> oriented silicon crystal.
 19. The sensor ofclaim 16 wherein the aspect ratio of the first substantially verticalsurface portions to the first generally horizontal surface portions isat least 5:1.
 20. The sensor of claim 16 wherein the aspect ratio of thefirst substantially vertical surface portions to the first generallyhorizontal surface portions is at least 20:1
 21. The sensor of claim 16, wherein said structure further includes two generally opposite facingsecond substantially vertical surface portions and two generallyopposite facing second generally horizontal surface portions; andwherein the aspect ratio of the first substantially vertical surfaceportions to the first generally horizontal surface portions differs fromthe aspect ratio of the second substantially vertical surface portionsto the second generally horizontal surface portions by at least 2:1. 22.The sensor of claim 16 wherein said first substantially vertical portionhas a height of at least 10 microns.
 23. A semiconductor sensorcomprising: a first single crystal silicon wafer layer; a single crystalsilicon structure formed in said first wafer layer and including twosubstantially vertical surfaces and two generally horizontal surfaceswherein a height of the vertical surfaces is substantially uniform andwherein a width of the horizontal surfaces is nonuniform; and a carrierincluding a recessed region wherein said carrier is secured to saidfirst wafer layer such that said structure is suspended opposite therecessed region.
 24. A semiconductor sensor comprising: a first singlecrystal silicon wafer layer; a plurality of single crystal siliconplates formed in said first wafer layer and having an aspect ratio of atleast 10:1; and a second single crystal wafer layer secured to saidfirst wafer layer such that said plates are suspended over the secondwafer layer.
 25. The sensor of claim 1 wherein, said second wafer layerdefines a recessed region and said plates are suspended opposite therecessed region.
 26. The sensor of claim 24 wherein said first layer andsaid second layer are fusion bonded together.
 27. The sensor of claim 24wherein said first layer is formed of <100> oriented silicon crystal.28. The sensor of claim 24 wherein each plate has a height of at least10 microns.
 29. A semiconductor sensor comprising: a first singlecrystal silicon wafer layer; a plurality of single crystal silicon beamsformed in said first wafer layer and having an aspect ratio of at least10:1; and a second single crystal wafer layer secured to said firstwafer layer such that said beams are suspended over the second waferlayer
 30. The sensor of claim 29 wherein, said second wafer layerdefines a recessed region and said beams re suspended opposite therecessed region.
 31. The sensor of claim 29 wherein said first layer andsaid second layer are fusion bonded together.
 32. The sensor of claim 29wherein said first layer is formed of <100> oriented silicon crystal.33. The sensor of claim 29 wherein at least one of said plurality ofbeams includes a plurality of vertical plates formed therein.
 34. Thesensor of claim 29 , wherein at least one of said plurality of bemasincludes a plurality of vertical plates formed therein; and wherein saidvertical plates have an aspect ratio of at least 10.1.
 35. The sensor ofclaim 29 , wherein at lest one of said plurality of beams includes aplurality of vertical plates formed therein; wherein said first waferlayer is formed of <100 oriented silicon crystal; and wherein saidvertical plates have an aspect ratio of at lest 10:1.
 36. The sensor ofclaim 29 , wherein at least one of said plurality of beams includes anelectronic circuit formed therein.
 37. The sensor of claim 29 , whereinat least one of said plurality of beams includes an electronic circuitformed therein; and wherein said first wafer layer is formed of <100>oriented silicon crystal.
 38. The sensor of claim 29 , wherein at leastone of said plurality of beans includes an electronic circuit formedtherein and further includes a plurality of vertical plates formedtherein.
 39. The sensor of claim 29 , wherein at least one of saidplurality of beams includes an electronic circuit formed therein andfurther includes a plurality of vertical plates formed therein; andwherein said first wafer layer is formed of <100> oriented siliconcrystal.
 40. The sensor of claim 29 , wherein at least one of saidplurality of beams includes an electronic circuit formed therein andfurther includes a plurality of vertical plates formed therein; andwherein said vertical plates have an aspect ratio of at least 10:1 41.The sensor of claim 29 , wherein at least one of said plurality of beamsincludes an electronic circuit formed therein and further includes aplurality of vertical plates formed therein; wherein said first waferlayer is formed of <100> oriented silicon crystal; and wherein saidvertical plates have an aspect ratio of at least 10:1.
 42. The sensor ofclaim 29 , wherein each beam has a height of at least 10 microns.
 43. Asemiconductor sensor produced by the steps of: providing a first singlecrystal silicon wafer layer; providing a carrier; including a recessedregion bonding the first wafer layer to the carrier with the recessedregion facing the first wafer layer; and etching substantiallyvertically through the first wafer layer opposite the recessed region ina curvilinear pattern so as to form a curvilinear structure integralwith the first wafer layer and suspended over the recessed region. 44.The product of claim 43 wherein the step of etching includes reactiveion etching.
 45. The product of claim 43 wherein the step of providingthe first wafer layer includes providing a single crystal <100> orientedsilicon wafer layer.
 46. The product of claim 43 wherein said processincludes the further step of thinning the first wafer layer to not lessthan ten microns.
 47. A semiconductor sensor produced by the steps of:providing a first single crystal silicon wafer layer, providing acarrier including a recessed region bonding the first wafer layer to thecarrier with the recessed region facing the first wafer layer; andetching substantially vertically through the first wafer layer oppositethe recessed region so as to form a beam integral with the first waferlayer and suspended over the recessed region wherein the beam has anaspect ratio of height to width of at least 5:1.
 48. The product ofclaim 47 wherein the step of etching includes reactive ion etching. 49.The product of claim 47 wherein the step of providing the first waferlayer includes providing a single crystal <100> oriented silicon waferlayer.
 50. The product of claim 47 wherein the step of etching includesetching substantially vertically through the first wafer layer oppositethe recessed region so as to form multiple beams integral with the firstwafer layer and suspended over the recessed region wherein each beam hasan aspect ratio of height to width of at least 10:1.
 51. A semiconductorsensor produced by the steps of: providing a first single crystalsilicon wafer layer providing a carrier including a recessed regionfusion bonding the first wafer layer to the carrier with the recessedregion facing the firs wafer layer; and etching substantially verticallythrough the first wafer layer opposite the recessed region so as to forma plate integral with the first wafer layer and suspended over therecessed region wherein the plate has an aspect ratio of height to widthof at least 5:1.
 52. The product of claim 51 wherein the step of etchingincludes reactive ion etching.
 53. The product of claim 51 wherein thestep of providing the first wafer layer includes providing a singlecrystal <100> oriented silicon wafer layer.
 54. The product of claim 51wherein the step of etching includes etching substantially verticallythrough the first wafer layer opposite the recessed region so as to formmultiple plates integrated with the first wafer layer and suspended overthe recessed region wherein each plate has an aspect ratio of height towidth of at least 10:1.